Certain field effect transistor devices known as thin film transistors are useful in the fabrication of various circuits including bistable flip-flops and static memory cells utilizing such flip-flops. FIG. 1 shows a typical static random access memory cell (referred to herein as an SRAM cell), generally designated by the reference numeral 10.
Static memory cell 10 generally comprises first and-second inverters 12 and 14 which are cross-coupled to form a bistable flip-flop. Inverters 12 and 14 are formed by n-channel driver or pull-down transistors 16 and 17, and p-channel load transistors 18 and 19. Driver transistors 16 and 17 are typically metal oxide silicon field effect transistors (MOSFETs) formed in an underlying silicon semiconductor substrate. This type of transistor is sometimes referred to as a "bulk" device because its active regions are formed in the bulk substrate. P-channel transistors 18 and 19 are typically thin film transistors formed above the driver transistors.
The source regions of driver transistors 16 and 17 are tied to a low reference or circuit supply voltage, labelled V.sub.ss and typically referred to as "ground." Load transistors 18 and 19 are connected in series between a high reference or circuit supply voltage, labelled V.sub.cc, and the drains of the corresponding driver transistors 16 and 17. The gates of load transistors 18 and 19 are connected to the gates of the corresponding driver transistors 16 and 17. The physical construction of many semiconductor memory cells allow a common transistor gate conductor to be used to gate corresponding driver and load transistors, as will be explained more fully below.
Inverter 12 has an inverter output 20 formed by the drain of driver transistor 16. Similarly, inverter 14 has an inverter output 22 formed by the drain of driver transistor 17. Inverter 12 has an inverter input 24 formed by the gate of driver transistor 16. Inverter 14 has an inverter input 26 formed by the gate of driver transistor 17.
The inputs and outputs of inverters 12 and 14 are cross-coupled to form a flip-flop having a pair of complementary two-state outputs. Specifically, inverter output 20 is cross-coupled to inverter input 26, and inverter output 22 is cross-coupled to inverter input 24. In this configuration, inverter outputs 20 and 22 form the complementary two-state outputs of the flip-flop.
A memory flip-flop such as that described typically forms one memory element of an integrated array of static memory elements. A plurality of access transistors, such as access transistors 30 and 32, are used to selectively address and access individual memory elements within the array. Access transistor 30 is an n-channel MOSFET having one active terminal connected to cross-coupled inverter output 20. Access transistor 32 is an n-channel MOSFET having one active terminal connected to cross-coupled inverter output 22. A plurality of complementary or "split" column line pairs, such as the single pair of column lines 34 and 36 shown, are connected to the remaining active terminals of access transistors 30 and 32, respectively. A row line 38 is connected to the gates of access transistors 30 and 32.
Reading static memory cell 10 requires activating row line 38 to connect inverter outputs 20 and 22 to column lines 34 and 36. Writing to static memory cell 10 requires first placing selected complementary logic voltages on column lines 34 and 36, and then activating row line 38 to connect those logic voltages to inverter outputs 20 and 22. This forces the outputs to the selected logic voltages, which will be maintained as long as power is supplied to the memory cell, or until the memory cell is reprogrammed.
FIG. 2 shows the physical structure of one prior art SRAM cell 40 utilizing thin film transistors. SRAM cell 40 includes a p-type silicon semiconductor substrate 42 and an oxide field isolation region 44. SRAM cell 40 also includes adjacent first and second transistor gate conductors 46 and 48. Each transistor gate conductor 46 and 48 performs several functions. For instance, transistor gate conductor 46 serves as a gate for an overlying thin film transistor which corresponds to load transistor 18 of FIG. 1, and also as a gate for an underlying bulk substrate transistor which corresponds to driver transistor 16 of FIG. 1. Transistor gate conductor 46 also serves as an interconnecting conductor between the gates of load transistor 18 and driver transistor 16. Similarly, transistor gate conductor 48 serves as a gate for an overlying thin film transistor which corresponds to load transistor 19 of FIG. 1, and also as a gate for an underlying bulk substrate transistor which corresponds to driver transistor 17 of FIG. 1. Transistor gate conductor 48 also serves as an interconnecting conductor between the gates of load transistor 19 and driver transistor 17.
As shown by FIG. 2, a discrete conductor 50 is formed adjacent first transistor gate conductor 46. A similar discrete conductor (not shown) is also formed adjacent second transistor gate conductor 48. These conductors correspond to row or word line 38 of FIG. 1. Access transistor 30 is formed beneath discrete conductor 50 in portions of the semiconductor substrate which are not shown by FIG. 2. FIG. 2 does show underlying active areas associated with driver transistors 16 and 17, designated by the reference numeral 52.
Each of gate conductors 46 and 48 is spaced from the underlying substrate by a gate oxide layer 54. Insulating sidewall spacers 56 are formed adjacent the sidewalls of gate conductors 46 and 48. Similar insulating spacers 58 are formed adjacent the sidewalls of discrete conductor 50. A thin insulating oxide layer 60 overlies the entire structure, forming a thin film transistor gate oxide above transistor gate conductors 46 and 48. Oxide layer 60 follows the contours of the gate conductors and the discrete conductor, resulting in deep valleys between conductors.
Thin film regions are provided over oxide layer 60 to form the channel, source, and drain regions of thin film transistors corresponding to load transistors 18 and 19 of FIG. 1. A thin film 62, shown in FIG. 2, forms load transistor 18 as shown in FIG. 1. Thin film 62 is formed over the gate oxide covering first gate conductor 46. It extends laterally over discrete conductor 50 and is insulated from discrete conductor 50 by oxide layer 60. Thin film 62 also extends laterally over and into electrical contact with second gate conductor 48. A portion of gate oxide layer 60 over second gate conductor 48 is removed and replaced with a thin conductive film 64 to allow this electrical contact. The right-hand side of thin film 62 is doped to form the source of load transistor 18, which is typically connected to V.sub.cc as described above with reference to FIG. 1. The left-hand side of thin film 62 is doped to form the drain of load transistor 18, and is connected to the gates of transistors 17 and 19 through conductive region 64.
The construction described above provides notable advantages over older, non-thin-film technology. However, increasing requirements for higher memory cell densities have begun to reveal shortcomings in existing fabrication methods. For instance, as memory and transistor densities increase, higher resolution is required of lithography equipment. This is typically achieved by increasing the numerical aperture of such equipment. However, increased aperture results in a correspondingly reduced depth of focus. The structure described above has what can be termed as severe topology, containing an overall variation in surface elevation or depth of over 2,500 Angstroms. This surface elevation variation imposes a limit on the degree of workable increase in the numerical aperture of lithography equipment, therefore limiting the achievable density of thin film transistors and memory circuits utilizing such transistors.
The severe topology of prior art SRAM constructions causes other practical difficulties in semiconductor processing. These problems result from the surface elevation or height steps in the various material layers associated with thin film formation. For instance, severe elevation steps often impose a requirement for an anti-reflective coating beneath applied photoresist. Application and presence of anti-reflective coatings creates numerous difficulties in subsequent processing relating primarily to the removal of the coatings. One such difficulty arises because of the unavailability of anti-reflective coating etching processes which are selective to either polysilicon or oxide. Thus, removing anti-reflective coatings from vertical surfaces can result in over-etching of thin underlying layers of polysilicon or oxide layers on horizontal surfaces.
Patterning of the polysilicon thin film is also difficult when the thin film is applied over severe topologies and elevation steps. This difficulty is due primarily to the anisotropic nature of preferred etching processes. During thin film etching, underlying thin layers of oxide are typically utilized as etch stops. However, anisotropically removing thin polysilicon layers lying along steep vertical surfaces requires extended periods of etching. Such extended etching can damage the thin oxide layers over horizontal surfaces.
The invention described below reduces or eliminates many of the difficulties discussed above.